Thin film transistors (TFTs) are electronic switching devices commonly used in active-matrix, flat-panel, electronic devices, such as an Active-Matrix, Liquid Crystal Displays (also known as an AMLCDs or, sometimes, a TFT-LCDs) or optical/X-ray Active-Matrix, Flat-Panel Imagers (also known as an AMFPI). The core active-matrix technology for display and imaging is basically the same. This technology utilizes a two-dimensional array of active electronic switching devices, such as TFTs, which are connected to gate lines and data lines to be selectively turned on and off to form a spatial display or to sense an image.
For image sensing electronics, each pixel usually includes a photodiode as an optical photodetector sensor connected to a pixel electrode. X-ray detection can also be performed by adding a phosphor layer above the photodiode sensor to convert received X-rays into optical photons for subsequent optical detection.
For display electronics, each pixel is associated with liquid crystals connected to the pixel electrode. The timing for TFT switching is often controlled by peripheral circuit drivers, which are typically implemented by crystalline silicon Complementary Metal-Oxide-Semiconductor (CMOS) Integrated Circuits (ICs) with interfacing bond wires connected to each gate line and each data line.
TFTs are considered to be good for active-matrix applications because the materials used in the manufacturing process, e.g., hydrogenated amorphous silicon (a-Si:H) and amorphous silicon nitride (a-SiNx:H), can be fabricated between 120 and 300° C., which is a thermal budget compatible with the commonly used substrate materials for active-matrix electronics, e.g., glass, plastic, ceramic, insulating-film-coated steel and insulating-film-coated semiconductor.
Currently, for large-area active-matrix imagers and displays, lithographic techniques are constrained to 5-μm or larger features (see, for example, T. Sandstrom and L. Odselius, Large-area high-quality photomasks, Proceedings of SPIE—Volume 2621, December 1995, pp. 312-318). This is due to stringent requirements of photo-etching precision and high yield on TFTs and interconnect-line processes for virtually flawless images and low manufacturing cost. Consequently, the advanced lithography for sub-micron to nano IC processes is usually not applicable to the production of large-area electronics. The channel length of the TFT may, therefore, be no shorter than about 5 μm and the overall area of the TFT (15×10 μm2), including the source electrode, gate electrode and drain electrode, may be determined from a length dimension that is approximately triple the 5 μm lithographic constraint and a width dimension that is at least double the 5 μm lithographic constraint.
In the traditional, lateral TFT design for pixelated active-matrix imagers, each TFT occupies part of the pixel area as a switch for the photo-sensor, see Y. Kuo, “Amorphous Silicon Thin Film Transistors,” Kluwer Academic Publishers, Norwell, Mass., 2003. As a result, TFT size imposes a limit to the array resolution, since the pixel fill factor, defined as a ratio of the photosensitive area to the pixel area, diminishes rapidly as pixel pitch is reduced below 100 μm.
The present solution to resolve this constraint on fill factor is by stacking a continuous layer of photo-sensitive material on top of the TFT matrix, see J. T. Rahn et al., High resolution X-ray imaging using amorphous silicon flat-panel arrays, IEEE Nucl. Sci. Symp. 1998, Conf. Rec., Vol. 2, pp. 1073-1077. However, since lateral TFTs always occupy some pixel area, in addition to that area occupied by the gate lines and the data lines, the degree to which pixel size may be reduced is limited by the size of the lateral TFT.
To eliminate the dependence of the channel length on the photolithography technique, a vertical TFT (i.e., a VTFT) structure has been proposed wherein channel material is oriented in the vertical direction. Rather that being laid out laterally, components of a VTFT are layered. In particular, a doped source ohmic contact layer and a similarly doped drain ohmic contact layer are stacked on either side of a dielectric in a sandwich structure. An active channel layer is provided along the side of the sandwich structure and a gate along the active channel layer. The thickness of the dielectric is then the determining factor for the length of the channel, rather than lithographic techniques. The proposed VTFT structure allows the channel length to be scaled down, below that allowed by lateral TFTs, to nanometer-scale (i.e., below 100 nm).
It can be shown that such a VTFT has a significant switching speed improvement over a lateral TFT counterpart. Advantageously, VTFTs allow the building of peripheral circuitry directly on the panel to replace CMOS ICs and interfacing overheads and, thereby, allow for a reduction in manufacturing cost. However, the proposed VTFT includes limiting factors for high-speed switching.
Accordingly, there remains a need for a compact TFT structure that reduces limiting factors for high-speed switching.